Integrated circuits are made up of millions of active devices formed in or on a silicon substrate. The active devices, which are initially isolated from one another, are interconnected to form functional circuits and components. The devices are interconnected through the use of well-known multilevel interconnections.
Interconnection structures normally have a first layer of metallization, an interconnection layer, a second level of metallization, and sometimes a third and subsequent level of metallization. Interlevel dielectrics, such as doped and undoped silicon dioxide (SiO.sub.2), are used to electrically isolate the different levels of metallization in a silicon substrate or well.
The electrical connections between different interconnection levels are made through the use of metallized vias. U.S. Pat. No. 4,789,648 describes a method for preparing multiple metallized layers and metallized vias in insulator films. In a similar manner, metal contacts are used to form electrical connections between interconnection levels and devices formed in a well. The metal vias and contacts may be filled with various metals and alloys (hereinafter referred to as "conductive metals"), such as titanium (Ti), titanium nitride (TiN), aluminum copper (Al--Cu), aluminum silicon (Al--Si), copper (Cu), tungsten (W), noble metals (e.g., iridium (Ir), ruthenium (Ru), gold (Au), and platinum (Pt)), and combinations thereof.
The metal vias and contacts generally employ an adhesion layer (hereinafter referred to as a "barrier film"), such as a titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) barrier film, to adhere the metal layer to the SiO.sub.2 substrate. At the contact level, the barrier film acts as a diffusion barrier to prevent the conductive metal and SiO.sub.2 from reacting.
In one semiconductor manufacturing process, metallized vias or contacts are formed by a blanket metal deposition followed by a chemical-mechanical polish (CMP) step. In a typical process, via holes are etched through an interlevel dielectric (ILD) to interconnection lines or to a semiconductor substrate. Next, a barrier film is formed over the ILD and is directed into the etched via hole. Then, a metal film is blanket-deposited over the barrier film and into the via hole. Deposition is continued until the via hole is filled with the blanket-deposited metal. Finally, the excess metal is removed by chemical-mechanical polishing (CMP) to form metal vias. Processes for manufacturing and/or CMP of vias are disclosed in U.S. Pat. Nos. 4,671,851, 4,910,155, and 4,944,836.
In a typical chemical-mechanical polishing process, the substrate to be polished is placed in direct contact with a rotating polishing pad. During the polishing process, the pad and substrate are rotated while a downward force is maintained on the substrate against the pad by a carrier. An abrasive and chemically reactive solution, commonly referred to as a "slurry," is applied to the pad during polishing. The slurry initiates the polishing process by chemically reacting with the substrate being polished, and the abrasive acts to mechanically polish the substrate. While the abrasive typically is in the slurry, the abrasive also can be fixed on the polishing pad. The polishing process is facilitated by the rotational movement of the pad relative to the substrate (i.e., plate speed) and/or the movement of the substrate relative to the pad (i.e., carrier speed), as a polishing composition is provided to the pad/substrate interface. Polishing is continued in this manner until the desired material on the substrate is removed.
The polishing composition is an important factor in the CMP process. Depending on the choice of the oxidizing agent, the abrasive, and other useful additives, the polishing composition can be tailored to provide effective polishing to metal layers at desired polishing rates while minimizing surface imperfections, defects, corrosion, and erosion. Furthermore, the polishing composition can be used to provide controlled polishing selectivities to specific materials used in integrated circuit technology. Accordingly, the polishing efficiency of particular polishing compositions is dependent upon the composition, as well as the chemical nature of the component metals in the vias (i.e., conductive metals) and the barrier films.
Barrier films of titanium, titanium nitride, and like metals, such as tungsten, are chemically active in general. Thus, such barrier films are similar in chemical nature to typical conductive metals, such as copper. Consequently, a single polishing composition can be used effectively to polish both Ti/TiN barrier films and Cu conductive metals at similar rates. Such polishing compositions typically contain an abrasive material, such as silica or alumina, suspended in an aqueous medium with an oxidizing agent, a film-forming agent, and/or other components. See, e.g., U.S. Pat. Nos. 5,726,099, 5,783,489, 5,858,813, and 5,954,997.
Tantalum barrier films, however, are significantly different from Ti, TiN, and like barrier films. Tantalum (Ta) and tantalum nitride (TaN) are relatively inert in chemical nature as compared to Ti and TiN. Accordingly, the aforementioned polishing compositions are significantly less effective at polishing tantalum layers than they are at polishing titanium layers (i.e., the tantalum removal rate is significantly lower than the titanium removal rate). While conductive metals and titanium are conventionally polished with a single composition due to their similarly high removal rates, joint polishing of conductive metals and tantalum results in undesirable effects such as oxide erosion and conductive metal dishing. These undesirable effects are due to the significantly higher removal rate of typical conductive metals than of tantalum during the polishing process with the aforementioned polishing compositions.
Consequently, there remains a need for a method of chemically-mechanically polishing a substrate comprising tantalum and a conductive metal (e.g., copper) in a manner such that planarization efficiency, uniformity, and removal rate are maximized and undesirable effects, such as surface imperfections and damage to underlying topography, are minimized. The present invention provides such a method. These and other characteristics and advantages of the present invention will be apparent from the description of the invention provided herein.